FPGA Deep-Capture
Logic Analyzer
Senior Design Project with Analog Devices
This project is an FPGA-based logic analyzer focused on reliable, long-duration digital capture rather than shallow on-chip debug buffers. The design combines configurable sampling and triggering with change-based compression, DDR/DRAM-backed storage, and processor-controlled data export so captured waveforms can be converted into standard analysis formats.
Design Priorities
- Preserve samples without data loss.
- Maximize usable sampling rate.
- Support a practical channel count and long capture depth.
- Reduce storage bandwidth with lossless compression.
- Keep the architecture modular enough for later synchronous/asynchronous modes.
System Architecture
Capture RTL
The FPGA datapath is organized as a set of independent blocks for channel selection, sampling, edge/change detection, timestamps, triggering, compression, packetization, and memory writes. The initial implementation uses a single FPGA clock domain to make timing behavior deterministic and simplify verification. A higher-rate asynchronous sampling mode is reserved as a later extension instead of complicating first bring-up.
Deep Storage
Short on-chip memories are not enough for long captures, so the architecture is designed around external DDR/DRAM. Raw or encoded capture records are packetized and moved through AXI into a ring-buffer-style memory region. This separates the real-time sampling path from slower storage and host-interface tasks.
Lossless Compression
For signals that remain unchanged across many sample periods, storing every repeated value wastes memory bandwidth. The planned encoder records transitions and run lengths with timestamps so the original waveform can be reconstructed without losing information. The compression path is optional: the memory system is designed so correctness does not depend on achieving a particular compression ratio.
Processor and Export Path
The system uses the Zynq UltraScale+ processing system alongside programmable logic. Bare-metal software on the ARM Cortex-A53 side handles capture control and file/storage operations, including moving completed captures to SD storage. The output path is intended to support standard waveform tooling through formats such as VCD, with USB/host integration as the project matures.
RTL Modules
| Block | Purpose |
|---|---|
| Channel Mux | Selects and groups active input channels. |
| Sampler | Captures input state on the configured sampling clock. |
| Trigger Engine | Arms capture and detects configured start conditions. |
| Edge / Change Detect | Determines when captured values change. |
| RLE + Timestamp Encoder | Creates compact, lossless capture records. |
| Packetizer | Formats records for the memory writer. |
| AXI DDR Writer | Moves capture data into external memory. |
| Control / Status Registers | Provides software-visible configuration and state. |
Current Development Stage
The project is in active development. The architecture, RTL/firmware partitioning, capture/storage data flow, and front-end plan are established, with board and processor bring-up feeding into incremental RTL implementation. Each block is being treated as a separately verifiable component before full-system integration.