FPGA “Hello World” — Zybo Z7 LED Blinky (SystemVerilog + XDC)

A blinky program is a quintessential first project when working with any new piece of hardware. This blinky program not only blinks an onboard LED on the Zybo Z7-10, but also uses the board’s switches to control the blinking speed.

This project was my first end-to-end Vivado flow: writing SystemVerilog RTL, creating XDC constraints for pin mapping and clock timing, generating a bitstream, and programming the FPGA on real hardware.

Demo Video

Schematic / Pin Mapping Reference

Blinky schematic / pin mapping

What I Implemented

  • Single-clock design: used the Zybo’s 125 MHz clock for all logic (no derived clocks).
  • Counter-based timing: counted clock cycles to generate human-visible blink intervals.
  • Switch-controlled rate: switches select the blink speed (power-of-two scaling).
  • XDC constraints: mapped ports to physical pins (clock, LEDs, switches) and defined the clock period for timing analysis.

Tools / Tech

SystemVerilog, Xilinx Vivado, XDC constraints, Zybo Z7-10 (Zynq-7000)