Zane Richards
RTL / FPGA Portfolio

Electrical & Computer Engineering student at The University of Tulsa focused on digital IC design, RTL/FPGA systems, verification, and computer architecture.
LinkedIn GitHub Resume (PDF)

Expected May 2027 · B.S. Electrical Engineering + B.S. Computer Engineering

Digital design from architecture to hardware bring-up.

I build RTL-heavy systems and take them through simulation, verification, synthesis, timing closure, FPGA integration, and lab validation. My recent work spans USB-PD protocol hardware, AES-GCM acceleration, a pipelined RV32I SoC, and a deep-capture FPGA logic analyzer.

SystemVerilogPrimary RTL language
20%FPGA logic reduction on AES-GCM
30%Latency reduction on AES-GCM
May 2027Graduation
SystemVerilog / Verilog VHDL AXI SVA CDC Vivado Quartus C / C++ Python
Aug. 2026 – May 2027

FPGA Deep-Capture Logic Analyzer

Senior design project with Analog Devices: an FPGA-based logic analyzer built for configurable sampling, triggering, compression, and long-duration waveform capture. The architecture uses FPGA capture logic with DDR/DRAM-backed storage and processor-controlled data export.

Digital InputsConfigurable front-end interface
Capture RTLSampling, grouping, trigger logic
CompressionChange-based / RLE pipeline
DDR / DRAMDeep waveform buffering
ProcessorStorage and host export
Experience

Recent Engineering Work

Analog Devices — Digital IC Design Engineer Intern

San Jose, CA · May 2026 – August 2026
  • Architected and implemented a USB Power Delivery 3.2 source/sink emulator in SystemVerilog/Verilog across PHY, protocol, policy/DPM, port control, reset, chunking, cable detection, VDM handling, and top-level RTL.
  • Added configurable protocol fault injection and firmware-controlled stress behavior, then validated the system with simulation, logic analyzers, and USB-PD protocol analyzers on FPGA hardware.
  • Designed and integrated an AES-GCM 128-bit FPGA decryption subsystem using AXI, BRAM, MicroBlaze/Zynq, SVA, coverage, CDC, synthesis, timing closure, and hardware validation; reduced logic utilization about 20% and latency about 30%.

ABB — Hardware Engineering Intern

Bartlesville, OK · May 2025 – August 2025
  • Developed synthesizable Verilog reset/control logic interfacing with voltage-supervisor ICs and verified operation in simulation and on hardware.
  • Built a board-level analog test platform that reduced test cycles from 30 minutes to 1 minute.
Dec. 2025

RV32I Pipelined SoC

SystemVerilog · Zybo Z7-10 · RISC-V

Designed a pipelined RV32I SoC with decode, ALU, register file, forwarding, load-use stalls, branch/jump flushing, dual-port BRAM, UART, LED MMIO, and FPGA bring-up.

Computer ArchitectureRTLFPGA
Nov. 2025

2.5A Sensored BLDC

Assembled sensored BLDC control PCB

Designed a compact STM32 + DRV8313 sensored BLDC control module with separated power domains, high-current routing, decoupling, protection, and board-level verification.

PCB DesignEmbeddedPower
Nov. 2025

Overcurrent Relay Protection

Overcurrent relay protection simulation

Built a MATLAB simulation of an IEC inverse-time overcurrent relay for a 13.8 kV feeder, generated TCC curves, and validated trip behavior across multiple fault types.

MATLABPower Systems
FPGA Bring-Up

Zybo Z7 RTL Bring-Up

SystemVerilog · Vivado · Zybo Z7-10

Built small FPGA bring-up designs to validate the board clock, reset, GPIO, UART, and the Vivado implementation flow before integrating larger RTL systems.

VivadoSystemVerilog